1. Field of the Invention
The present invention relates to a semiconductor memory device, and, in particular, to a semiconductor memory device employing a hierarchical bit line configuration.
2. Description of the Related Art
Since capacity of semiconductor memory devices have increased in recent years, the number of memory cells connected to a pair of bit-lines is increasing. Accordingly, parasitic capacitance of bit lines is also increasing, thus lowering an operating speed.
In addition, when data is read from a memory cell that is connected to bit lines with an increased parasitic capacitance, it is necessary to sense output signals with small amplitude from the bit lines. For this purpose, a sense amplifier with small input offsets is required and a larger area needs to be provided as a region for forming the sense amplifiers.
However, developments in semiconductor memory devices are in trends of further refinements and integrations. It is against such trends to form a large-sized sense amplifier in semiconductor memory devices.
Therefore, in order to prevent reduction in operating speed and to provide as large amplitudes to be sensed as possible, certain configurations are proposed for dividing a memory cell array into a plurality of cell arrays in column direction. Such configurations may reduce the number of memory cells to be connected to a pair of bit lines and thereby reduce the capacity provided by the bit lines. Those configurations include hierarchical bit lines; one bit line that is connected to a memory cell in each cell array is called a “local bit line”, and toe other common bit line that corresponds to a plurality of cell arrays is called “a global bit line”. One of the semiconductor memory devices so configured is described, e.g., in Japanese Patent Laid-Open Publication Nos. 2005-166098 and 2005-267686.